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- PA0 â â1 TIM2. VT1
- PA1 â â2 TIM2. VT2
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èŠããããŸãããéã®é åºã§ããuint16_t sin_data[240] =
{13,26,39,52,65,78,91,104,117,130,143,156,169,182,195,207,220,233,246,258,
271,284,296,309,321,333,346,358,370,382,394,406,418,430,442,453,465,477,488,500,
511,522,533,544,555,566,577,587,598,608,619,629,639,649,659,669,678,688,697,707,
716,725,734,743,751,760,768,777,785,793,801,809,816,824,831,838,845,852,859,866,
872,878,884,891,896,902,908,913,918,923,928,933,938,942,946,951,955,958,962,965,
969,972,975,978,980,983,985,987,989,991,993,994,995,996,997,998,999,999,999,1000,
999,999,999,998,997,996,995,994,993,991,989,987,985,983,980,978,975,972,969,965,
962,958,955,951,946,942,938,933,928,923,918,913,908,902,896,891,884,878,872,866,
859,852,845,838,831,824,816,809,801,793,785,777,768,760,751,743,734,725,716,707,
697,688,678,669,659,649,639,629,619,608,598,587,577,566,555,544,533,522,511,500,
488,477,465,453,442,430,418,406,394,382,370,358,346,333,321,309,296,284,271,258,
246,233,220,207,195,182,169,156,143,130,117,104,91,78,65,52,39,26,13};
6.2ãã¯ããã¯ã·ã¹ãã ã®ã»ããã¢ãã
STM32ã§ã®ã¯ããã¯ã®èšå®ã¯éåžžã«æè»ã§äŸ¿å©ã§ãããããã€ãã®åŸ®åŠãªéãããããŸããã·ãŒã±ã³ã¹èªäœã¯æ¬¡ã®ãšããã§ãã1ïŒå
èµRCãã§ãŒã³ïŒHSIïŒããå€éšã¯ãªãŒãïŒHSEïŒãžã®ã¯ãããã³ã°ã«åãæ¿ããŠãããæºåå®äºãã©ã°ãåŸ
ã¡ãŸãRCC->CR |= ((uint32_t)RCC_CR_HSEON); // Enable HSE
while (!(RCC->CR & RCC_CR_HSERDY)); // Ready start HSE
2ïŒã³ã³ãããŒã©ãŒã®ãã©ãã·ã¥ã¡ã¢ãªã¯ã«ãŒãã«ãããããã«é
ãããããã©ãã·ã¥ã®ã¿ã€ãã³ã°ãæ§æããŸãããããè¡ããªããšãããã°ã©ã ã¯èµ·åããŸããã宿çã«äœäžããŸããæ°ããã¯ãããšäžå®å®ãªãœãããŠã§ã¢ã¯äºææ§ããããŸãããFLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; // Cloclk Flash memory
3ïŒã·ã¹ãã ã¯ããã¯ãã¹ïŒAHBïŒããã³ããªãã§ã©ã«ãã¹ã®ååšåšãèšå®ããŸãããããã®ãã¹ã«ã¯ãã§ã«APB1ãšAPB2ã®2ã€ã®éšåããããŸããæå€§é »åºŠãå¿
èŠãªã®ã§ãäœãé€ç®ãããä¿æ°ã1ã§é€ç®ããŸããRCC->CFGR |= RCC_CFGR_HPRE_DIV1; // AHB = SYSCLK/1
RCC->CFGR |= RCC_CFGR_PPRE1_DIV1; // APB1 = HCLK/1
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; // APB2 = HCLK/1
4ïŒåšæ³¢æ°éååšïŒPLLïŒãèšå®ãããã®åã«ç«ã£ãŠæ°Žæ¶åšæ³¢æ°ã2ã§é€ç®ããããªãã£ãã€ããŒãèšå®ããŸãã8MHzã2ã§é€ç®ãã4 MHzãåä¿¡ããŸãããæ¬¡ã«ãåºåã24 MHzã«ãªãããã«6ãæããå¿
èŠããããŸããã¬ãžã¹ã¿ãæžã蟌ãåã«ã念ã®ããæåã«ãã®å
å®¹ãæ¶å»ããŠãã ãããRCC->CFGR &= ~RCC_CFGR_PLLMULL; // clear PLLMULL bits
RCC->CFGR &= ~RCC_CFGR_PLLSRC; // clearn PLLSRC bits
RCC->CFGR &= ~RCC_CFGR_PLLXTPRE; // clearn PLLXTPRE bits
RCC->CFGR |= RCC_CFGR_PLLSRC_PREDIV1; // source HSE
RCC->CFGR |= RCC_CFGR_PLLXTPRE_PREDIV1_Div2; // source HSE/2 = 4 MHz
RCC->CFGR |= RCC_CFGR_PLLMULL6; // PLL x6: clock = 4 MHz * 6 = 24 MHz
5ïŒæ¬¡ã«ãåšæ³¢æ°éååšïŒPLLïŒããªã³ã«ããŠãæºåå®äºãã©ã°ãåŸ
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èŠããããŸããRCC->CR |= RCC_CR_PLLON; // enable PLL
while((RCC->CR & RCC_CR_PLLRDY) == 0) {} // wait till PLL is ready
6ïŒæåŸã«ãåšæ³¢æ°éååšã®ã·ã¹ãã ãã¹ïŒAHBïŒåºåã®ã¯ããã¯ãœãŒã¹ãæ§æããŸãããŸããã¬ãžã¹ã¿ã®å
容ãã¯ãªã¢ããç®çã®ããããèšå®ããŠãæºåå®äºãã©ã°ãåŸ
ã¡ãŸããRCC->CFGR &= ~RCC_CFGR_SW; // clear SW bits
RCC->CFGR |= RCC_CFGR_SW_PLL; // select source SYSCLK = PLL
while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1) {} // wait till PLL is used
ãã®çµæãã¯ããã¯ãèšå®ããããã®æ¬¡ã®é¢æ°ãååŸããŸããvoid RCC_Init (void){
RCC->CR |= ((uint32_t)RCC_CR_HSEON); // Enable HSE
while (!(RCC->CR & RCC_CR_HSERDY)); // Ready start HSE
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; // Cloclk Flash memory
RCC->CFGR |= RCC_CFGR_HPRE_DIV1; // AHB = SYSCLK/1
RCC->CFGR |= RCC_CFGR_PPRE1_DIV1; // APB1 = HCLK/1
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; // APB2 = HCLK/1
RCC->CFGR &= ~RCC_CFGR_PLLMULL; // clear PLLMULL bits
RCC->CFGR &= ~RCC_CFGR_PLLSRC; // clearn PLLSRC bits
RCC->CFGR &= ~RCC_CFGR_PLLXTPRE; // clearn PLLXTPRE bits
RCC->CFGR |= RCC_CFGR_PLLSRC_PREDIV1; // source HSE
RCC->CFGR |= RCC_CFGR_PLLXTPRE_PREDIV1_Div2; // source HSE/2 = 4 MHz
RCC->CFGR |= RCC_CFGR_PLLMULL6; // PLL x6: clock = 4 MHz * 6 = 24 MHz
RCC->CR |= RCC_CR_PLLON; // enable PLL
while((RCC->CR & RCC_CR_PLLRDY) == 0) {} // wait till PLL is ready
RCC->CFGR &= ~RCC_CFGR_SW; // clear SW bits
RCC->CFGR |= RCC_CFGR_SW_PLL; // select source SYSCLK = PLL
while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1) {} // wait till PLL is used
}
6.3ãTIM1ã¿ã€ããŒãšãããã¿ã€ã ã®ââèšå®
äžè¬çãªã¿ã€ããŒèšå®ã«ã€ããŠèª¬æããŸãã詳现ã¯ãªãã¡ã¬ã³ã¹ããã¥ã¢ã«ã«èšèŒãããŠããŸããåã¬ãžã¹ã¿ã®ç®çãèªãããšããå§ãããŸããã¯ããã€ã³ã¿ãŒãããã§PWMãæäœããããã®åºæ¬çãªèšäºããããŸããã³ãŒãèªäœã¯éåžžã«ããã³ã¡ã³ããããŠããã®ã§ãããã«ã¿ã€ããŒåæå颿°TIM1ã®ã³ãŒããæäŸããæãè峿·±ãç¹ãåæããŸããvoid PWM_50Hz_Init (void){
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable clock for TIM1
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; // enable clock for port A
RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; // enable clock for port B
RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for alternative gpio
/****************************** Setting PA10 **************************************/
GPIOA->CRH &= ~GPIO_CRH_CNF10; // setting out alternative push-pull for PWM
GPIOA->CRH |= GPIO_CRH_CNF10_1;
GPIOA->CRH &= ~GPIO_CRH_MODE10;
GPIOA->CRH |= GPIO_CRH_MODE10; // gpio speed 50 MHz
/***************************** Setting PB15 ***************************************/
GPIOB->CRH &= ~GPIO_CRH_CNF15; // setting complementary for CH3N
GPIOB->CRH |= GPIO_CRH_CNF15_1;
GPIOB->CRH &= ~GPIO_CRH_MODE15;
GPIOB->CRH |= GPIO_CRH_MODE15; // gpio speed 50 MHz
/************************** Config PWM channel ************************************/
TIM1->PSC = 480-1; // div for clock: F = SYSCLK / [PSC + 1]
TIM1->ARR = 1000; // count to 1000
TIM1->CR1 &= ~TIM_CR1_CKD; // div for dead-time: Tdts = 1/Fosc = 41.6 ns
TIM1->CCR3 = 500; // duty cycle 50%
TIM1->CCER |= TIM_CCER_CC3E | TIM_CCER_CC3NE; // enable PWM complementary out
TIM1->CCER &= ~TIM_CCER_CC3NP; // active high level: 0 - high, 1 - low
TIM1->CCMR2 &= ~TIM_CCMR2_OC3M;
TIM1->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1; // positiv PWM
TIM1->BDTR &= ~TIM_BDTR_DTG; // clear register
TIM1->BDTR |= TIM_BDTR_DTG_2 | TIM_BDTR_DTG_1 | TIM_BDTR_DTG_0; // value dead-time
TIM1->BDTR |= TIM_BDTR_MOE | TIM_BDTR_AOE; // enable generation output
/*******************************************************************************/
TIM1->CR1 &= ~TIM_CR1_DIR; // count up: 0 - up, 1 - down
TIM1->CR1 &= ~TIM_CR1_CMS; // aligned on the front signal
TIM1->CR1 |= TIM_CR1_CEN; // start count
}
åœç€Ÿã®ä¿¡é Œæ§ã¯åºå®ãããŠãããåšæ³¢æ°ã®ããã«å€åããããšã¯ãããŸããã察è§ç·ã®æéãšã·ãŒã±ã³ã¹ãèšå®ããã®ã¯ãã®ã¿ã€ããŒã§ãïŒTIM1->CCR3 = 500; // duty cycle 50%
ããããã¿ã€ã ãã®äžæåæ¢ã®æéã¯ãããã§èšå®ãããTDTSæéãã©ã¡ãŒã¿ã«å€§ããäŸåããŸããTIM1->CR1 &= ~TIM_CR1_CKD; // div for dead-time: Tdts = 1/Fosc = 41.6 ns
ãã®æéã¯1ãã£ãã¯ã®ã¯ããã¯åšæ³¢æ°ã§ãããªãã¡ã¬ã³ã¹ããã¥ã¢ã«ãèŠããšãCKDãããã«ãã£ãŠãããšãã°ãTdtsã2ã8ãã£ãã¯ãªã©ã«çãããªãããšãããããŸããéåžžã«äžæåæ¢ããæéã¯ããã§èšå®ãããŸãïŒTIM1->BDTR |= TIM_BDTR_DTG_2 | TIM_BDTR_DTG_1 | TIM_BDTR_DTG_0;
ãªãã¡ã¬ã³ã¹ããã¥ã¢ã«RM0041ãéããšãDTãèšç®ããããã®ãã®ãããªåŒã衚瀺ãããŸããã芧ã®ãšãããTdtsãã©ã¡ãŒã¿ãŒã¯åºæ¬çãªãã®ã§ãã
6.4ããµã€ã³ã圢æããããã®TIM2ã¿ã€ããŒã®èšå®
ããã§ã¯ãŸã ç°¡åã§ããã³ã¡ã³ãã¯ãã§ã«åé·ã§ãããããã»ããã¢ããã§äœãã説æããçç±ã¯ãããããªãã§ããããã質åãããå Žåã¯ãã³ã¡ã³ãã§ãåŸ
ã¡ããŠããŸããvoid PWM_Sinus_Init (void){
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // enable clock for TIM2
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; // enable clock for port A
RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; // enable clock for alternative gpio
/****************************** Setting PA0 ***************************************/
GPIOA->CRL &= ~GPIO_CRL_CNF0; // setting out alternative push-pull for PWM1_CH1
GPIOA->CRL |= GPIO_CRL_CNF0_1;
GPIOA->CRL &= ~GPIO_CRL_MODE0;
GPIOA->CRL |= GPIO_CRL_MODE0; // gpio speed 50 MHz
/****************************** Setting PA1 ***************************************/
GPIOA->CRL &= ~GPIO_CRL_CNF1; // setting out alternative push-pull for PWM1_CH1
GPIOA->CRL |= GPIO_CRL_CNF1_1;
GPIOA->CRL &= ~GPIO_CRL_MODE1;
GPIOA->CRL |= GPIO_CRL_MODE1; // gpio speed 50 MHz
/*************************** Config PWM channel ***********************************/
TIM2->PSC = 0; // div for clock: F = SYSCLK / [PSC + 1]
TIM2->ARR = 1000; // count to 1000
TIM2->CCR1 = 0; // duty cycle 0%
TIM2->CCR2 = 0; // duty cycle 0%
TIM2->CCER |= TIM_CCER_CC1E; // enable PWM out to PA8
TIM2->CCER &= ~TIM_CCER_CC1P; // active high level: 0 - high, 1 - low
TIM2->CCER |= TIM_CCER_CC2E; // enable PWM complementary out to PA9
TIM2->CCER &= ~TIM_CCER_CC1P; // active high level: 0 - high, 1 - low
TIM2->CCMR1 &= ~(TIM_CCMR1_OC1M | TIM_CCMR1_OC2M);
TIM2->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 |
TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1; // positiv PWM1_CH1 and PWM1_CH2
/*******************************************************************************/
TIM2->CR1 &= ~TIM_CR1_DIR; // count up: 0 - up, 1 - down
TIM2->CR1 &= ~TIM_CR1_CMS; // aligned on the front signal: 00 - front; 01, 10, 11 - center
TIM2->CR1 |= TIM_CR1_CEN; // start count
}
6.5ãTIM6ã¿ã€ããŒå²ã蟌ã¿ã®èšå®
ã¿ã€ããŒèªäœã24 kHzã®åšæ³¢æ°ã§æ§æããŸããvoid TIM6_step_init (void){
RCC->APB1ENR |= RCC_APB1ENR_TIM6EN; // enable clock for basic TIM6
TIM6->PSC = 1-1; // div, frequency 24 kHz
TIM6->ARR = 1000; // count to 1000
TIM6->DIER |= TIM_DIER_UIE; // enable interrupt for timer
TIM6->CR1 |= TIM_CR1_CEN; // start count
NVIC_EnableIRQ(TIM6_DAC_IRQn); // enable interrupt TIM6_DAC_IRQn
}
6.6ãåºæ¬çãªå¶åŸ¡ã¢ã«ãŽãªãºã ã®å®è£
äž»èŠãªã€ãã³ãã¯ãTIM6ã¿ã€ããŒã«ãã£ãŠçæãããå²ã蟌ã¿ã§çºçããŸããããããµã³ããªã³ã°æé ã§ããããšãèŠããŠããã°ã41.66ÎŒsããšã«å²ã蟌ã¿ãçæãããŸãããããã£ãŠãå²ã蟌ã¿ã§ã¯ããã¥ãŒãã£ãµã€ã¯ã«å€ãããŒãã«ããCCRxã¬ãžã¹ã¿ã«æžã蟌ãŸããŸãããŸãããã®å²ã蟌ã¿ã§ã¯ãåååšæåŸã«sin_statusãã©ã°ãå転ããããšã«ãããçŸåšã©ã®å¯Ÿè§ç·ãæç»ãããŠããããæ±ºå®ãããŸãã240ãã€ã³ãã衚瀺ãããã©ã°ãå転ããŸããããã«ãããã³ã³ãããŒã«ãå¥ã®ãã£ãã«ã«åãæ¿ããããŸãããã§ã«æç»ãããŠããå Žåããã©ã°ã¯åã³å転ããããã¹ãŠãç¹°ãè¿ãããŸããã¡ã€ã³ã¢ã«ãŽãªãºã ã®ã³ãŒãïŒvoid TIM6_DAC_IRQHandler(void){
TIM6->SR &= ~TIM_SR_UIF;
if(sin_status == 0){TIM2->CCR1 = sin_data[sin_step];}
if(sin_status == 1){TIM2->CCR2 = sin_data[sin_step];}
sin_step++;
if(sin_step >= 240){
sin_step=0;
sin_status = sin_status ? 0 : 1;
}
}
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